The present invention relates to tools and methods for finding every usage of a leaf cell which is considered the lowest level of artwork abstraction for a semiconductor design within a parent cell, or many parent cells, in a piece of semiconductor artwork and for determining where METAL 1 is used in the parent cell(s). The tools and methods of the present invention provide the ability to move and change the METAL 1 layers such that they may be used in a different piece of semiconductor artwork with the same footprint without affecting the ability of the parent cells to function.
Semiconductor artwork can be thought of as a pattern generated to make semiconductor-based electronic devices. Leaf cells are the smallest level of sub-components included in a piece of artwork and the METAL 1 (or first metal layer) of a typical leaf cell 5 is illustrated in FIG. 1. The leaf cell 5 would typically also include active, substrate and polysilicon areas that are not shown in FIG. 1. The typical leaf cell 5 in FIG. 1 implements a simple logic function containing four pieces of METAL 1 within a leaf cell boundary 10. The four pieces of METAL 1 are labeled A, Z, VDD and GND and represent an input 20, an output 30, a power supply 40 and a ground 50, respectively. FIG. 2 illustrates another typical, yet more complex, piece of semiconductor artwork that includes many leaf cells 5 used to form a more intricate design. FIG. 2 also illustrates many small pieces of METAL 1 foreign to the leaf cell itself.
A leaf cell 5 that is positioned as it appears in FIG. 1 is illustrated in one corner of FIG. 2 (Norm). FIG. 2 also illustrates other leaf cells 5 that have been rotated 90xc2x0 (r90), mirrored across the x-axis (mx), mirrored across the y-axis (my), mirrored across both the x- and y-axes (mxy) and/or xe2x80x9csteppedxe2x80x9d to form horizontal or vertical series of leaf cells 5. Although the artwork of FIG. 2 is representative of typical semiconductor artwork, other leaf cell and artwork geometries are also known to those skilled in the art.
Parent cells are levels of artwork abstraction that are formed by the combination of different leaf cells and that are therefore more complex than leaf cells. Different levels/orders/complexities of parent cells can exist within a single piece of artwork and allow the artwork to be thought of as a hierarchical structure. For example, FIG. 2 illustrates a first-order parent cell 60 and the leaf cells 5 can be thought of as being part of the first-order parent cell 60 since they are within the first-order parent cell boundary 70.
FIG. 3A illustrates leaf cells 80 (LC) that are part of first-order parent cells such as subblockA1 90, subblockA2 100, and subblockA3 110. FIG. 3B illustrates that subblockA1 90, subblockA2 100, and subblockA3 110 make up blockA 120, a larger, or second-order parent cell. FIG. 3C illustrates that, in turn, blockA 120 makes up, along with blockB 130 and blockC 140, a third-order parent cell, Chip1 150. This hierarchy continues until the highest-order parent cell, the device itself, is reached. The leaf cells 80 are the basic building blocks, the first-level parent cells 90, 100, 110 are slightly larger building blocks, and increasingly larger building blocks can also exist within the artwork. FIGS. 3A-3B illustrate a 3-level hierarchy of a chip design. However, higher levels of hierarchy are also typically used in semiconductor designs.
Much complex semiconductor artwork can be constructed by hierarchical methods wherein the sub-components (leaf cells and lower-level parent cells) are designed once and then simply reproduced repeatedly at various locations until the ultimate device is formed. In many situations, it is also desirable for device designers to use the same leaf cells or parent cells in different pieces of artwork. However, transferring (or porting) leaf cells between different fabrication processes with different design rules and/or transferring parent cells between one piece of artwork and another has, to date, proven to be problematic. Making the porting process more efficient would therefore make artwork design more efficient and would reduce overall fabrication costs of devices.
The terms xe2x80x9cportingxe2x80x9d and xe2x80x9cconvertingxe2x80x9d are clarified at this point in order to avoid ambiguities. The terms xe2x80x9cportingxe2x80x9d and xe2x80x9cconvertingxe2x80x9d refer to taking a design from process A (with design rules A) and converting them to process B (with design rules B) while still having the same functionality and electrical robustness to ensure that the design will work.
Currently, when a component of one piece of artwork is ported and integrated into another piece of artwork, an extensive amount of de-bugging, design-rule checking and trial-and-error testing is required to make the new artwork operable. This is true because, when a leaf cell is used in the new piece of artwork, there is a high probability that the METAL 1 layer in the leaf cell, if moved during the porting process, will overlap with at least a portion of the METAL 1 layer in the new artwork, causing a design rule violation where the leaf cell is used. As the number of leaf cells that are ported increases or the amount of METAL 1 moved within a leaf cell increases, so does the probability that design rules will have been violated. For example, when porting of artwork occurs at the lowest levels (e.g., substrate areas, active areas, polysilicon areas, etc.) of MOSFET designs, the METAL 1 layer routing must frequently be changed in the new design because of the new design rules (i.e. overlap of METAL 1 to active contact may increase, requiring an increase in the size of the METAL 1).
Hence, what is needed are tools and methods for finding every usage of a leaf cell within parent cell(s) in a piece of semiconductor artwork and for determining where METAL 1 is used in the parent cell or many parent cells.
What is also needed are tools and methods that provide the ability to move and change the METAL 1 layers such that they may be used in different pieces of semiconductor artwork without affecting the ability of the new piece of artwork to function in its previous footprint.
Certain embodiments of the present invention are directed at a script that finds every usage of a leaf cell and then indicates where metal appears within the leaf cell""s boundary at all of these instances.
Certain embodiments of the present invention are also directed at methods of transferring a piece of artwork from one device to another that reduce the workload involved in de-bugging and rules-testing that is typically associated with the process.
Certain embodiments of the present invention are directed at methods for taking a piece of artwork from one device, inspecting every single use where the artwork is used, and building a composite block of its environment. Then, with the composite block of the environment, it is possible to determine what can be safely changed without conflicting with other components in parent cells.
Certain embodiments of the present invention are directed at computer programs that process computer data used to control the manufacturing equipment that mass-produces micro-electronic devices. The programs search for specific pieces of artwork and their associated composite blocks.